In recent years, attention has been paid to the application of a bidirectional switching element to a direct link conversion circuit, such as a matrix converter which performs, for example, AC (alternating current)/AC conversion, AC/DC (direct current) conversion, and DC/AC conversion in a semiconductor power conversion device, in terms of a reduction in the size and weight of a circuit, an increase in the efficiency of the circuit, a high speed response, and low costs.
The matrix converter has a higher power conversion efficiency than an inverter/converter. In general, the inverter/converter generates a DC intermediate voltage from an AC power supply and converts the intermediate voltage into an AC voltage. However, the matrix converter directly generates the AC voltage from the AC power supply, without generating the intermediate voltage.
In addition, since an electrolytic capacitor is used as a capacitor for generating the intermediate voltage in the inverter/converter, there is a problem that the life span of the device is determined by the life span of the electrolytic capacitor. In contrast, in the matrix converter, it is not necessary to provide the capacitor for generating the intermediate voltage between the AC power supply and an AC voltage output unit. Therefore, it is possible to avoid the problem of the inverter/converter.
FIGS. 29 and 30 are equivalent circuit diagrams illustrating a matrix converter according to the related art. As described above, a bidirectional switching element in which a current can flow bi-directionally is used as a power device which is used in the matrix converter. The bidirectional switching element is not formed by a single element, but includes, for example, two diodes 101 and two transistors 102, as illustrated in FIG. 29.
In the bidirectional switching element illustrated in FIG. 29, the diode 101 is provided in order to maintain the breakdown voltage of the power device when a reverse voltage is applied to the transistor 102. This is because a general IGBT (Insulated Gate Bipolar Transistor) or MOSFET (Metal Oxide Semiconductor Field Effect Transistor) which is used as the transistor 102 cannot ensure the reverse breakdown voltage.
In recent years, a reverse blocking IGBT (RB-IGBT: Reverse Blocking IGBT) has been developed which ensures the breakdown voltage even when the reverse voltage is applied. The bidirectional switching element includes, for example, two reverse blocking IGBTs 103 as illustrated in FIG. 30. The bidirectional switching element illustrated in FIG. 30 has a smaller number of elements than the bidirectional switching element illustrated in FIG. 29. Therefore, the bidirectional switching element has low power loss and the total size of the elements is small. Therefore, when the bidirectional switching element illustrated in FIG. 30 is applied to the matrix converter, it is possible to provide a matrix converter with a small size and low costs.
As the bidirectional switching element using the reverse blocking IGBT, an element with a reverse breakdown voltage has been proposed in which a MOS gate structure including a gate electrode and an emitter electrode is provided on one surface of an n− drift layer, which is a semiconductor substrate having a GaN (gallium nitride) semiconductor or an SiC (silicon carbide) semiconductor as a main semiconductor crystal, a cutting plane used to cut the semiconductor substrate into chips includes a p-type protective region which connects the front and rear surfaces of the n− drift layer, and a collector electrode which comes into contact with the rear surface of the n− drift layer includes a Schottky metal film (for example, see the following Patent Literature 1).
The reverse blocking IGBT includes reverse blocking capability which is substantially the same as forward blocking capability. In the reverse blocking IGBT, in order to ensure the reverse blocking capability, a pn junction is formed by a diffusion layer (hereinafter, referred to as a separation layer) which extends from the rear surface to the front surface of the semiconductor chip through the drift layer and separates the side surface of the semiconductor chip and the drift layer. The pn junction maintains the reverse breakdown voltage of the reverse blocking IGBT.
Next, a method of forming the separation layer will be described. FIGS. 31 to 35 are cross-sectional views illustrating a method of manufacturing a reverse blocking IGBT with silicon according to the related art. Here, a method will be described which diffuses a dopant from an impurity source (liquid diffusion source) coated on a semiconductor wafer (coating diffusion method) to form a diffusion layer which will be a separation layer. First, for example, an oxide film 112 is formed on the front surface of an n-type semiconductor wafer 111 by thermal oxidation (FIG. 31).
The thickness of the oxide film 112 is, for example, about 2.5 μm. Then, an opening portion 113 for forming the separation layer is formed in the oxide film 112 by photolithography to form a mask oxide film 114 for a dopant mask (FIG. 32). Then, a boron (B) source 115 is coated on the mask oxide film 114 so as to fill the opening portion 113.
Then, the semiconductor wafer 111 is put into a diffusion furnace and a heat treatment is performed for the semiconductor wafer 111 at a high temperature for a long time to form a p-type diffusion layer 116 in a surface layer of the front surface of the semiconductor wafer 111 (FIG. 33). The thickness of the diffusion layer 116 is, for example, about several hundreds of micrometers. In the subsequent process, the diffusion layer 116 becomes the separation layer.
Then, a front surface element structure 117 (see FIG. 35) of the reverse blocking IGBT is formed on the front surface of the semiconductor wafer 111. Then, the rear surface of the semiconductor wafer 111 is ground until the diffusion layer 116 is exposed and the semiconductor wafer 111 is thinned (FIG. 34). Then, a rear surface element structure including a p collector region 118 and a collector electrode 119 is formed on the ground rear surface of the semiconductor wafer 111 (FIG. 35).
Then, the semiconductor wafer 111 is diced into chips along scribe lines (not illustrated) which are formed at the center of the diffusion layer 116. In this way, as illustrated in FIG. 35, a reverse blocking IGBT in which the separation layer, which is the diffusion layer 116, is formed on a cut plane 120 of the chip is completed.
FIGS. 36 to 39 are cross-sectional views illustrating another example of the method of manufacturing the reverse blocking IGBT with silicon according to the related art. Here, a method will be described in which a trench (groove) is formed in a semiconductor wafer and a diffusion layer which will be a separation layer is formed on the side surface of the trench. First, for example, an oxide film 122 with a thickness of about several micrometers is formed on the front surface of an n-type semiconductor wafer 121 by, for example, thermal oxidation (FIG. 36).
Then, a trench 123 is formed in the front surface of the semiconductor wafer 121 by dry etching (FIG. 37). The trench 123 has a depth of, for example, about several hundreds of micrometers. In this case, an opening portion 124 with the same with as the trench 123 is formed in the oxide film 122 to form a mask oxide film 125 for a dopant mask.
Then, impurities 126 are implanted into the bottom and side wall of the trench 123 by a vapor-phase diffusion method to form an impurity layer 127 on the bottom and side wall of the trench 123 (FIG. 38). In the subsequent process, the impurity layer 127 becomes the separation layer. Then, a front surface element structure is formed on the front surface of the semiconductor wafer 121, the rear surface of the semiconductor wafer 121 is ground until the impurity layer 127 is exposed, and a rear surface element structure is formed on the ground surface (FIG. 39).
Then, the trench 123 is filled with a reinforcing material 128 and the semiconductor wafer 121 is diced into chips along scribe lines. The scribe lines are formed at positions where the semiconductor wafer 121 can be diced along the center of the trench 123. In this way, as illustrated in FIG. 39, a reverse blocking IGBT is completed in which the separation layer, which is the impurity layer 127, is formed on a cut plane 129 of the chip.
The following method using silicon has been proposed as a method of forming the separation layer on the side wall of the trench. A substrate which is made of a first-conduction-type semiconductor material and has a second-conduction-type epitaxial layer formed thereon is prepared. Then, a first-conduction-type second region is formed in the upper surface of the epitaxial layer and a trench which passes through the epitaxial layer from the upper surface of the second region, reaches the substrate, and surrounds an active layer is formed. Then, first-conduction-type impurities are implanted into the side wall of the trench and an annealing process is performed to form a low-resistance path which electrically connects the second region and the substrate (for example, see the following Patent Literature 2).
As another method using silicon, the following method has been proposed. A groove which reaches the pn junction between an n base region and a p collector region is formed outside a portion which will be a guard ring structure. Then, a surface layer of the groove is removed (etched) by a chemical process. In this case, the bottom of the groove after etching is so deep as to traverse the pn junction. A p region which comes into contact with a p collector region in the rear surface of the substrate and a p region in the front surface of the substrate is formed from the surface of the groove (for example, see the following Patent Literature 3).
As another method using silicon, a method has been proposed in which a P layer is formed on the side wall of an N base layer so as to come into contact with a P collector layer and an outer circumferential portion of a breakdown voltage structure (for example, see the following Patent Literature 4).
In the method of manufacturing the reverse blocking IGBT illustrated in FIGS. 31 to 34, when the separation layer (diffusion layer 116) with a diffusion depth of about several hundreds of micrometers is formed, a diffusion process needs to be performed at a high temperature for a long time. Therefore, a quartz jig, such as a quartz board, a quartz pipe (quartz tube), or a quartz nozzle forming a diffusion furnace, deteriorates, contaminants are received from a heater, or the strength of the quartz jig is reduced by devitrification.
In addition, it is necessary to form a high-quality and thick mask oxide film 114 with resistance to the diffusion process which is performed at a high temperature for a long time (for example, 1300° C. and 200 hours). For example, the thickness of the mask oxide film 114 needs to be about 2.5 μm such that boron does not penetrate the mask oxide film 114 in the diffusion process. In order to form a thermally-oxidized film with a thickness of about 2.5 μm, it is necessary to perform thermal oxidation, for example, at a temperature of 1150° C. for 200 hours using a dry (dry oxygen atmosphere) oxidation method.
A wet oxidation method or a pyrogenic oxidation which has film quality slightly lower than the dry oxidation method, but has a processing time shorter than that the dry oxidation method requires a processing time of about 15 hours. In addition, since a large amount of oxygen is introduced into the semiconductor wafer during the oxidation process, an oxygen precipitate is generated, a crystal defect, such as an oxidation induced stacking fault (OSF), is introduced, or an oxygen donor is generated. As a result, the characteristics of the device deteriorate or the reliability of the device is reduced.
In the dry oxidation method, since the diffusion process is generally performed in an oxidation atmosphere at a high temperature for a long time as described above, oxygen is introduced between the grids in the semiconductor wafer and an oxygen precipitate is generated, an oxygen donor is generated, or a crystal defect, such as an oxidation induced stacking fault or slip dislocation, is introduced. As a result, a leakage current in the pn junction increases, the breakdown voltage or reliability of the insulating film formed on the semiconductor wafer is significantly reduced. In addition, oxygen introduced into the semiconductor wafer changes to a donor during the diffusion process and the breakdown voltage is reduced.
In the method of manufacturing the reverse blocking IGBT illustrated in FIGS. 31 to 34, boron is substantially isotropically diffused from the opening portion 113 of the mask oxide film 114. Therefore, when boron is diffused about 200 μm in the depth direction, it is also diffused about 180 μm in the lateral direction, which prevents a reduction in a device pitch or a chip size.
In the method of manufacturing the reverse blocking IGBT illustrated in FIGS. 36 to 39, the trench with a high aspect ratio is formed and the separation layer is formed on the side wall of the trench. Therefore, it is possible to reduce the device pitch, as compared to the method of manufacturing the reverse blocking IGBT illustrated in FIGS. 31 to 34. However, the time required to form a trench with a depth of about 200 μm in the semiconductor wafer using the typical dry etching device is about 100 minutes per wafer. Therefore, the lead time increases or the number of maintenance operations for the dry etching device increases.
When a deep trench is formed by the dry etching process using a silicon oxide film (SiO2) mask, a silicon oxide film with a thickness of about several micrometers is needed since the selectivity of the mask is equal to or less than about 50. As a result, manufacturing costs increase, a process-induced crystal defect, such as an oxidation induced stacking fault or an oxygen precipitate, is introduced, or the yield rate is reduced.
When the trench with a high aspect ratio is formed by dry etching, the following problems arise. FIG. 40 is a cross-sectional view illustrating a main portion of the reverse blocking IGBT according to the related art during a manufacturing process. As illustrated in FIG. 40, for example, a resist residue 131 or a chemical residue 132 is likely to be generated in the trench 123. As a result, yield or reliability is reduced.
In general, in the introduction of a dopant, such as phosphorus (P) or boron, into the side wall of the trench, since the side wall of the trench is vertical, the semiconductor wafer is inclined and ions are implanted into the inclined semiconductor wafer to introduce the dopant into the side wall of the trench. However, when impurities are introduced into the trench with a high aspect ratio, the ion implantation method is not appropriate, for example, since the effective dose is reduced, the implantation time increases due to the reduction in the effective dose, the effective projection range is narrowed, the dose is reduced due to a screen oxide film, or implantation uniformity is reduced.
Therefore, instead of the ion implantation method, a vapor-phase diffusion method is used in which a semiconductor wafer is exposed to a gaseous impurity atmosphere, such as phosphine (PH3) or diborane (B2H6). However, the vapor-phase diffusion method is worse than the ion implantation method in terms of accurately controlling the dopant dose. In the vapor-phase diffusion method, in many cases, the dose of the dopant to be introduced is restricted by a solubility limit and the performance of accurately controlling the dopant dose is lower than that in the ion implantation method.
When the aspect ratio of the trench is high and the trench is filled with the insulating film, an empty space which is called a void, is likely to be generated in the trench and reliability is reduced. In addition, in the manufacturing methods disclosed in Patent Literature 2 to Patent Literature 4, when the semiconductor wafer is diced into the individual chips, it is considered that a process of filling the trench with, for example, a reinforcing material, is needed, which results in an increase in manufacturing costs.
As a method for solving the above-mentioned problems, the following method using silicon has been proposed. FIGS. 41 and 42 are cross-sectional views illustrating the reverse blocking IGBT according to the related art. In a semiconductor chip 140 including a side surface 141 which is tapered such that the width thereof increases from the emitter to the collector as illustrated in FIG. 41 or a semiconductor chip 150 including a side surface 151 which is tapered such that the width thereof increases from the collector to the emitter as illustrated in FIG. 42, impurity ions are implanted into the tapered side surface 141 or 151 and annealing is performed to form a separation layer 142 or 152 (for example, see Patent Literature 5).
As a method of processing the side surface of the semiconductor chip in a tapered shape, a method using silicon has been proposed which selectively removes a portion of a semiconductor wafer using anisotropic etching (for example, see the following Patent Literature 6 and the following Patent Literature 7).
In the reverse blocking IGBT with the tapered side surface 151 whose width increases from the collector to the emitter as illustrated in FIG. 42, it is possible to widely use the emitter-side main surface, as compared to the reverse blocking IGBT including the tapered side surface 141 illustrated in FIG. 41. Therefore, it is possible to increase the width of an emitter region or a channel region which is formed in a surface layer of the emitter-side main surface and thus manufacture a reverse blocking IGBT with high current density. In addition, it is possible to manufacture a reverse blocking IGBT which has the same current rating as that according to the related art and a smaller chip area than that according to the related art.
In the reverse blocking IGBTs illustrated in FIGS. 41 and 42, impurity ions are implanted into the tapered side surfaces 141 and 151 and annealing is performed to form the separation layers 142 and 152. Therefore, the diffusion process illustrated in FIGS. 31 to 34 which is performed at a high temperature for a long time is not needed. As a result, a crystal defect or a defect caused by oxygen does not occur in the semiconductor wafer or the diffusion furnace does not deteriorate.
In addition the aspect ratio of the groove formed by the tapered side surface 141 or 151 is lower than that of the trench (see FIGS. 36 to 39). Therefore, it is possible to simply introduce a dopant using ion implantation, without generating a void or a residue (see FIG. 40) in the tapered side surface 141 or 151.